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PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
FEATURES * * * * * * 19MHz to 65MHz crystal input. Output range: 9.5MHz - 65MHz Selectable OE Logic (enable high or enable low). Available outputs: PECL, LVDS, or CMOS (High Drive (30mA) or Standard Drive (10mA) output). Supports 2.5V or 3.3V Power Supply. Available in die form. DIE CONFIGURATION
OUTSEL0^
65 mil
OUTSEL1^
Reserved
VDD
VDD
VDD
VDD
N/C
(1550,1475)
17 16
25
24
23
22
21
20
19
18
GNDBUF CMOS LVDSB PECLB VDDBUF VDDBUF PECL LVDS OE_SEL^
XIN XOUT N/C
62 mil
26
27
Die ID: A2020-20B
15
28
14
DESCRIPTION The PLL620-80 is a XO IC specifically designed to work with fundamental or 3 rd OT crystals between 19MHz and 65MHz. The selectable divide by two feature extends the operation range from 9.5MHz to 65MHz. It requires very low current into the crystal resulting in better overall stability. The OE logic feature allows selection of enable high or enable low. Furthermore, it provides selectable CMOS, PECL or LVDS outputs.
S2^ OE CTRL N/C
13 29 12
11 30
C502A
31 1 2 3 4 5 6 7 8
10 9
Reserved
Y
(0,0)
X
OUTPUT SELECTION AND ENABLE
OUT_SEL1* (Pad 18) 0 0 1 1 OE_SELECT (Pad 9) 0 1 (Default) OUT_SEL0* (Pad 25) 0 1 0 1 OE_CTRL (Pad 30) 0 1 (Default) 0 (Default) 1 Selected Output* High Drive CMOS Standard CMOS LVDS PECL (default) State Tri-state Output enabled Output enabled Tri-state
DIE SPECIFICATIONS
Name Size Reverse side Pad dimensions Thickness Value 62 x 65 mil GND 80 micron x 80 micron 10 mil
BLOCK DIAGRAM
OE Q XIN XOUT
Oscillator Amplifier
Q S2
PLL620-80
Pads #9, #18 & #25: Bond to GND to set to "0", No connection results to "default" setting through internal pull-up. OE_CTRL: Logical states defined by PECL levels if OE_SELECT is "1" Logical states defined by CMOS levels if OE_SELECT is "0"
OUTPUT FREQUENCY SELECTOR
S2 0 1(Default)*
*Internally set to `Default' through 60K
Output Input/2 Input
pull-up resistor
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 1
GNDBUF
GNDBUF
GND
GND
GND
GND
GND
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model
SYMBOL
VDD VI VO TS TA TJ
MIN.
-0.5 -0.5 -65 -40
MAX.
4.6 VDD+0.5 VDD+0.5 150 85 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications PARAMETERS
Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Recommended ESR
SYMBOL
FXIN CL (xtal) C0 RE
CONDITIONS
Fundamental Die AT cut
MIN.
19
TYP.
8*
MAX.
65 5 30
UNITS
MHz pF pF
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
3. General Electrical Specifications PARAMETERS
Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current
SYMBOL
IDD VDD
CONDITIONS
PECL/LVDS/CMOS @ 50% VDD (CMOS) @ 1.25V (LVDS) @ VDD - 1.3V (PECL)
MIN.
2.97 45 45 45
TYP.
MAX.
100/80/40 3.63 55 55 55
UNITS
mA V % mA
50 50 50 50
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 2
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
4. Jitter Specifications PARAMETERS
Period jitter RMS at 27MHz Period jitter peak-to-peak at 27MHz Accumulated jitter RMS at 27MHz Accumulated jitter peak-to-peak at 27MHz Random Jitter
Measured on Wavecrest SIA 3000
CONDITIONS
With capacitive decoupling between VDD and GND. Over 10,000 cycles With capacitive decoupling between VDD and GND. Over 1,000,000 cycles. "RJ" measured on Wavecrest SIA 3000
MIN.
TYP.
2.3 18.5 2.3 24 2.3
MAX.
20 25
UNITS
ps ps ps
5. Phase Noise Specifications PARAMETERS
Phase Noise relative to carrier
FREQUENCY
27MHz
@10Hz
-75
@100Hz
-100
@1kHz
-125
@10kHz
-140
@100kHz
-145
UNITS
dBc/Hz
Note: Phase Noise measured on Agilent E5500
6. CMOS Output Electrical Specifications PARAMETERS
Output drive current (High Drive) Output drive current (Standard Drive) Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive)
SYMBOL
IOH IOL IOH IOL
CONDITIONS
VOH= VDD-0.4V, VDD=3.3V VOL = 0.4V, VDD = 3.3V VOH= VDD-0.4V, VDD=3.3V VOL = 0.4V, VDD = 3.3V 0.3V ~ 3.0V with 15 pF load 0.3V ~ 3.0V with 15 pF load
MIN.
30 30 10 10
TYP.
MAX.
UNITS
mA mA mA mA
2.4 1.2
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 3
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
7. LVDS Electrical Characteristics PARAMETERS
Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current
SYMBOL
VOD VOD VOH VOL VOS VOS IOXD IOSD
CONDITIONS
MIN.
247 -50
TYP.
355 1.4 1.1 1.2 3 1 -5.7
MAX.
454 50 1.6 1.375 25 10 -8
UNITS
mV mV V V V mV uA mA
RL = 100 (see figure)
0.9 1.125 0
Vout = VDD or GND VDD = 0V
8. LVDS Switching Characteristics PARAMETERS
Differential Clock Rise Time Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
tr tf
CONDITIONS
RL = 100 CL = 10 pF (see figure)
MIN.
0.2 0.2
TYP.
0.7 0.7
MAX.
1.0 1.0
UNITS
ns ns
LVDS Switching Test Circuit
OUT CL = 10pF
50
VOD
VOS
VDIFF
RL = 100
50
CL = 10pF OUT
OUT
LVDS Transistion Time Waveform
OUT 0V (Differential) OUT
80% VDIFF 20% 0V
80%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 4
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
9. PECL Electrical Characteristics PARAMETERS
Output High Voltage Output Low Voltage
SYMBOL
VOH VOL
CONDITIONS
RL = 50 to (VDD - 2V) (see figure)
MIN.
VDD - 1.025
MAX.
VDD - 1.620
UNITS
V V
10. PECL Switching Characteristics PARAMETERS
Clock Rise Time Clock Fall Time
SYMBOL
tr tf
PECL Levels Test Circuit
CONDITIONS
@20/80% - PECL @80/20% - PECL
MIN.
TYP.
0.6 0.5
MAX.
1.5 1.5
UNITS
ns ns
PECL Output Skew
VDD OUT
OUT
50
2.0V 50%
50 OUT OUT tSKEW
PECL Transistion Time Waveform
DUTY CYCLE 45 - 55% 55 - 45%
OUT 80% 50% 20% OUT tR tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 5
PLL620-80
PAD DESCRIPTIONS
Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name GND GND Optional GND GND GND Reserved GNDBUF GNDBUF OE_SEL LVDS PECL VDDBUF VDDBUF PECLB LVDSB CMOS GNDBUF OUTSEL1 Reserved Not connected VDD Optional VDD VDD VDD OUTSEL0 XIN XOUT Not connected S2 OE_CTRL Not connected X (m) 248 361 473 587 702 874 1042 1171 1400 1400 1400 1400 1400 1400 1400 1400 1389 1232 1042 854 659 559 459 358 194 109 109 109 109 109 109
Low Phase Noise XO (9.5-65MHz Output)
Y (m) 109 109 109 109 109 109 109 109 125 259 476 616 716 871 1089 1227 1365 1365 1365 1365 1365 1365 1365 1365 1365 1223 1017 858 646 397 181 Ground. Ground. Optional Ground. Ground. Ground. Reserved for future use. Ground, buffer circuitry. Ground, buffer circuitry. This is the selector input to choose the OE control logic. See the OE SELECTION AND ENABLE table on page 1. Internal pull up. LVDS output. PECL output. Power supply, buffer circuitry. Power supply, buffer circuitry. Complementary PECL output. Complementary LVDS output. CMOS output. Ground, buffer circuitry. Selector input to choose the selected output type (PECL, LVDS, CMOS). See the OUTPUT SELECTION AND ENABLE table on page 1. Internal pull up. Reserved for future use. Not Connected. Power supply. Optional Power supply. Power supply. Power supply. Selector input to choose the selected output type (PECL, LVDS, CMOS). See the OUTPUT SELECTION AND ENABLE table on page 1. Internal pull up. Crystal input. See Crystal Specifications on page 3. Crystal output. See Crystal Specifications on page 3. Not Connected. Output Divide by Two selector pin, as presented on the OUTPUT FREQUENCY SELECTOR Table on page 1. Internal pull up. Used to enable/disable the output(s). See Output Selection and Enable table on page 1. Not connected. Description
Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 6
PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PART NUMBER
PLL620-80
PART NUMBER
DC
TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE D=DIE
Order Number PLL620-80DC
Marking P620-80DC
Package Option Die - Waffle Pack
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 7

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